R-Car H3 - Renesas - WikiChip (2024)

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R-Car H3
General Info
Designer	Renesas, ARM Holdings
Manufacturer	TSMC
Model Number	H3
Part Number	R8A77950
Market	Embedded
Introduction	December 2, 2015 (announced) March, 2018 (launched)
General Specs
Family	R-Car
Series	3rd Gen
Microarchitecture
ISA	ARMv8(ARM)
Microarchitecture	Cortex-A53, Cortex-A57, Cortex-R7
Core Name	Cortex-A53, Cortex-A57, Cortex-R7
Process	16 nm
Technology	CMOS
Die	111.36 mm² 12.94 mm × 8.61 mm
Word Size	64 bit
Cores	9
Threads	9
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	0.8 V
VI/O	3.3 V
Packaging
Package FCBGA-1384 (BGA) Dimension 21 mm x 21 mm Pitch 0.50 mm Ball Count 1384 Interconnect BGA-1384

R-Car H3 is a 64-bit nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and a dual-core lock-step Cortex-R7 for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the Imagination's PowerVR GX6650 GPU.

Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019.

Cache[edit]

Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache

Cortex-A57 Cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144B 0.25MiB L1I$ 128 KiB 131,072B 0.125MiB 4x48 KiB L1D$ 128 KiB 131,072B 0.125MiB 4x32 KiB L2$ 2 MiB 2,048KiB 2,097,152B 0.00195GiB 1x2 MiB

Cortex-A53 Cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144B 0.25MiB L1I$ 128 KiB 131,072B 0.125MiB 4x32 KiB L1D$ 128 KiB 131,072B 0.125MiB 4x32 KiB L2$ 512 KiB 0.5MiB 524,288B 4.882812e-4GiB 1x512 KiB

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4-3200 Supports ECC No Controllers 1 Channels 4 Width 32 bit Max Bandwidth 47.68 GiB/s 48,824.32MiB/s 51.196GB/s 51,196.01MB/s 0.0466TiB/s 0.0512TB/s Bandwidth Single 11.92 GiB/s Double 23.84 GiB/s Quad 47.68 GiB/s

Expansions[edit]

• PCI Express2.0 (1 lane) x 2 ch
• USB 3.0 Host interface (DRD) × 1 ports (wPHY)
• USB 2.0 Host/Function/OTG interface × 2 ports (wPHY)
• SD Host interface × 4 ch (SDR104)
• Multimedia card interface × 2 ch
• Serial ATA interface × 1 ch
• Media local bus (MLB) Interface × 1 ch (3 pin interface)
• Controller Area Network (CAN-FD support) Interface × 2ch
• Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
• SYS-DMAC x 48 ch, Realtime-DMAC x 16 ch,
• Audio-DMAC x 32 ch, Audio(peripheral)-DMAC x 29 ch
• 32bit timer x 26 ch
• PWM timer × 7 ch
• I2C bus interface × 7 ch
• Serial communication interface (SCIF) × 11 ch
• Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support)
• Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
• Ethernet controller (IEEE802.3u, RMII, without PHY)
• Digital radio interface (DRIF) × 4 ch

Graphics[edit]

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR GX6650 Designer Imagination Technologies

Features[edit]

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	VFPv4 Vector Floating Point (VFP) v4 Extension NEON Advanced SIMD extension TrustZone TrustZone Security Extensions

Block Diagram[edit]

Die[edit]

• 16 nm process, CMOS FinFET
• 12.94 mm × 8.61 mm
• 111.36 mm² die size
• Quad-core Cortex-A53
  • ~3.27 mm² cluster
  • ~0.60 mm² core
  • ~0.7`mm² L2 cache
• Quad-core Cortex-A57
  • ~10.21 mm² cluster
  • ~1.66 mm² core
  • ~3.28 mm² L2 cache
• Cortex-R7 (dual-core lock-step)
  • ~1.04 mm² cluster
• GX6650 GPU
  • ~28.12 mm²

Bibliography[edit]

• Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10− 7 random hardware failures per hour reliability." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
• Shibahara, Shinichi, et al. "A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard." IEEE Journal of Solid-State Circuits 52.1 (2017): 77-88.